mirror of https://github.com/proxmox/mirror_qemu
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-4-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
parent
86d916c621
commit
ebfdc49428
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@ -264,6 +264,25 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
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}
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}
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}
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}
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static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
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{
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XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
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uint64_t ret = 0;
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if (!fifo32_is_empty(&s->fdro_data)) {
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ret = fifo32_pop(&s->fdro_data);
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}
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return ret;
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}
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static void cfu_fdro_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported write from addr=%"
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HWADDR_PRIx "\n", __func__, addr);
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}
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static const MemoryRegionOps cfu_stream_ops = {
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static const MemoryRegionOps cfu_stream_ops = {
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.read = cfu_stream_read,
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.read = cfu_stream_read,
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.write = cfu_stream_write,
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.write = cfu_stream_write,
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@ -274,6 +293,16 @@ static const MemoryRegionOps cfu_stream_ops = {
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},
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},
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};
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};
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static const MemoryRegionOps cfu_fdro_ops = {
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.read = cfu_fdro_read,
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.write = cfu_fdro_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void cfu_apb_init(Object *obj)
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static void cfu_apb_init(Object *obj)
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{
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
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@ -305,6 +334,39 @@ static void cfu_apb_init(Object *obj)
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sysbus_init_irq(sbd, &s->irq_cfu_imr);
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sysbus_init_irq(sbd, &s->irq_cfu_imr);
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}
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}
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static void cfu_fdro_init(Object *obj)
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{
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XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem_fdro, obj, &cfu_fdro_ops, s,
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TYPE_XLNX_VERSAL_CFU_FDRO, KEYHOLE_STREAM_4K);
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sysbus_init_mmio(sbd, &s->iomem_fdro);
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fifo32_create(&s->fdro_data, 8 * KiB / sizeof(uint32_t));
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}
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static void cfu_fdro_reset_enter(Object *obj, ResetType type)
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{
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XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
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fifo32_reset(&s->fdro_data);
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}
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static void cfu_fdro_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
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{
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XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(cfi_if);
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if (fifo32_num_free(&s->fdro_data) >= ARRAY_SIZE(pkt->data)) {
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for (int i = 0; i < ARRAY_SIZE(pkt->data); i++) {
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fifo32_push(&s->fdro_data, pkt->data[i]);
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}
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} else {
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/* It is a programming error to fill the fifo. */
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qemu_log_mask(LOG_GUEST_ERROR,
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"CFU_FDRO: CFI data dropped due to full read fifo\n");
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}
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}
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static Property cfu_props[] = {
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static Property cfu_props[] = {
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DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
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DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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@ -351,6 +413,16 @@ static const VMStateDescription vmstate_cfu_apb = {
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}
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}
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};
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};
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static const VMStateDescription vmstate_cfu_fdro = {
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.name = TYPE_XLNX_VERSAL_CFU_FDRO,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_FIFO32(fdro_data, XlnxVersalCFUFDRO),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void cfu_apb_class_init(ObjectClass *klass, void *data)
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static void cfu_apb_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -360,6 +432,17 @@ static void cfu_apb_class_init(ObjectClass *klass, void *data)
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device_class_set_props(dc, cfu_props);
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device_class_set_props(dc, cfu_props);
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}
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}
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static void cfu_fdro_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass);
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dc->vmsd = &vmstate_cfu_fdro;
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xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
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rc->phases.enter = cfu_fdro_reset_enter;
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}
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static const TypeInfo cfu_apb_info = {
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static const TypeInfo cfu_apb_info = {
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.name = TYPE_XLNX_VERSAL_CFU_APB,
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.name = TYPE_XLNX_VERSAL_CFU_APB,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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@ -372,9 +455,22 @@ static const TypeInfo cfu_apb_info = {
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}
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}
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};
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};
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static const TypeInfo cfu_fdro_info = {
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.name = TYPE_XLNX_VERSAL_CFU_FDRO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxVersalCFUFDRO),
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.class_init = cfu_fdro_class_init,
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.instance_init = cfu_fdro_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_XLNX_CFI_IF },
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{ }
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}
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};
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static void cfu_apb_register_types(void)
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static void cfu_apb_register_types(void)
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{
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{
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type_register_static(&cfu_apb_info);
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type_register_static(&cfu_apb_info);
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type_register_static(&cfu_fdro_info);
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}
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}
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type_init(cfu_apb_register_types)
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type_init(cfu_apb_register_types)
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@ -20,10 +20,14 @@
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/register.h"
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#include "hw/misc/xlnx-cfi-if.h"
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#include "hw/misc/xlnx-cfi-if.h"
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#include "qemu/fifo32.h"
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#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
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#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
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#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
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REG32(CFU_ISR, 0x0)
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REG32(CFU_ISR, 0x0)
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FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
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FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
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FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
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FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
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@ -210,6 +214,14 @@ struct XlnxVersalCFUAPB {
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} cfg;
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} cfg;
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};
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};
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struct XlnxVersalCFUFDRO {
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SysBusDevice parent_obj;
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MemoryRegion iomem_fdro;
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Fifo32 fdro_data;
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};
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/**
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/**
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* This is a helper function for updating a CFI data write fifo, an array of 4
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* This is a helper function for updating a CFI data write fifo, an array of 4
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* uint32_t and 128 bits of data that are allowed to be written through 4
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* uint32_t and 128 bits of data that are allowed to be written through 4
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