mirror of https://github.com/proxmox/mirror_qemu
target/riscv: Add instructions of the Zbc-extension
The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
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@ -3,6 +3,7 @@
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*
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
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* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
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{
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return do_gorc(rs1, rs2, 32);
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}
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target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
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{
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target_ulong result = 0;
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for (int i = 0; i < TARGET_LONG_BITS; i++) {
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if ((rs2 >> i) & 1) {
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result ^= (rs1 << i);
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}
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}
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return result;
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}
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target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
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{
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target_ulong result = 0;
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for (int i = 0; i < TARGET_LONG_BITS; i++) {
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if ((rs2 >> i) & 1) {
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result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
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}
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}
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return result;
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}
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@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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/* Special functions */
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DEF_HELPER_2(csrr, tl, env, int)
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@ -714,6 +714,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
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greviw 0110100 .......... 101 ..... 0011011 @sh5
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gorciw 0010100 .......... 101 ..... 0011011 @sh5
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# *** RV32 Zbc Standard Extension ***
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clmul 0000101 .......... 001 ..... 0110011 @r
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clmulh 0000101 .......... 011 ..... 0110011 @r
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clmulr 0000101 .......... 010 ..... 0110011 @r
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# *** RV32 Zbs Standard Extension ***
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bclr 0100100 .......... 001 ..... 0110011 @r
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bclri 01001. ........... 001 ..... 0010011 @sh
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@ -1,5 +1,5 @@
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/*
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* RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
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* RISC-V translation routines for the Zb[acs] Standard Extension.
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*
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
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@ -24,6 +24,12 @@
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} \
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} while (0)
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#define REQUIRE_ZBC(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZBS(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
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return false; \
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@ -535,3 +541,27 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
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REQUIRE_ZBA(ctx);
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
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}
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static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
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{
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REQUIRE_ZBC(ctx);
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return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
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}
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static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
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{
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gen_helper_clmulr(dst, src1, src2);
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tcg_gen_shri_tl(dst, dst, 1);
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}
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static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
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{
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REQUIRE_ZBC(ctx);
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return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
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}
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static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
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{
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REQUIRE_ZBC(ctx);
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return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
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}
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